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International Journal of Communication and Information Technology

Impact Factor (RJIF): 5.56, P-ISSN: 2707-661X, E-ISSN: 2707-6628
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2025, Vol. 6, Issue 2, Part C

Design of an area efficient RISC-V SoC for En/Decryption acceleration for Homomorphic Encryption


Author(s): Kalisetty Sreeja and Saidaiah Bandi

Abstract:

Edge devices often connect to the cloud these days so they can use its storage and processing power. This brings up concerns about the safety and privacy of user data. Homomorphic encryption (HE) is a good way to protect data privacy because it lets you do any kind of elegant computation on encrypted data without ever needing to decrypt it. There have been a lot of attempts to make HE computations in the cloud faster, but less attention has been paid to the methods of converting messages to ciphertext and ciphertext to messages on the edge. This work profiles the edge-side conversion procedures, and our analysis shows that the encryption, decryption, and error sampling activities are the main problems that slow down the conversion process. To get around these problems, we present RISE, a RISCV SoC that uses less space and energy. RISE uses a lightweight and effective pseudorandom number generator core along with fast sampling methods to speed up the error sampling processes. The number theoretic transform operation is the main bottleneck in the encryption and decryption processes. RISE speeds up these processes by using scalable, data-level parallelism. Also, RISE uses strategies like memory reuse and data reordering to use as little on-chip memory as possible. It also saves space by using a single en/decryption datapath. We use a full RTL design with a RISC-V processor that is connected to our accelerator to test RISE. Our research shows that using RISE instead of just the RISC-V processor makes converting messages to ciphertext and ciphertext to messages much more energy-efficient, by up to 6191.19× and 2481.44×, respectively



DOI: 10.33545/2707661X.2025.v6.i2c.162

Pages: 210-213 | Views: 113 | Downloads: 44

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International Journal of Communication and Information Technology
How to cite this article:
Kalisetty Sreeja, Saidaiah Bandi. Design of an area efficient RISC-V SoC for En/Decryption acceleration for Homomorphic Encryption. Int J Commun Inf Technol 2025;6(2):210-213. DOI: 10.33545/2707661X.2025.v6.i2c.162
International Journal of Communication and Information Technology

International Journal of Communication and Information Technology

International Journal of Communication and Information Technology
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